The present invention relates generally to integrated circuits (ICs) and more particularly, to power supply management within ICs.
Electronic devices such as laptops, mobile phones, and computers function based on the operation of several ICs. The demand for reduction in the dimensions and increased speed has sparked several developments in semiconductor technology that have resulted in considerable miniaturization of ICs and device sizes. The increasing complexity and high frequency operations have resulted in ICs having high dynamic and static power consumption. The static power is dissipated when the IC is in low power mode, e.g., stand-by, sleep mode, idle and hibernate, while the dynamic power consumption occurs when the chip performing tasks. For devices powered by batteries, static and dynamic power consumption are critical parameters because high power consumption drains the battery quickly. However, for circuits that remain in the low power mode for most of their life, such as the ICs used in the automobile safety systems, reducing static power consumption is more crucial than reduction in dynamic power consumption.
Static power consumption is due to leakage current and sub-threshold current flowing in the transistors of the IC. Therefore, reducing the leakage current will reduce the static power consumption. Several techniques, such as biasing the sources of the transistors (source biasing) or biasing the body of the transistors (well biasing), have been used for reducing leakage current in applications other than automotive applications. However, the hostile environment of an automobile (attributed to high engine temperature, mechanical vibration, dust, etc.), has hampered the usage of the above-mentioned techniques due to low power supply rejection ratios (PSRR) of power regulators inside the ICs. The low values of PSRR may be attributed to high values (in the order of millilamperes (mA)) of leakage currents drawn by the IC during the low power modes. The high leakage currents are a result of high operating temperature of the IC (highly probable in an automobile environment) or when clocks received by the IC are configured to remain switched on in the low power mode to run basic time keeping functions.
Due to the low PSRR, the output power provided to an array of source biased memory cells (which are combinations of n-type and p-type metal oxide semiconductor field effect transistors (NMOS and PMOS)) may have an irregular voltage profile. The magnitude of the glitches in the voltage profile may be more than the noise margin of the memory cells. It is known that source biasing increases the threshold voltage (Vt) of an NMOS transistor. Therefore, when the supply voltage drops, the probability of the PMOS transistor pulling the memory cell from zero to one increases, which flips the memory cell. Thus, to implement source biasing in a noisy environment, the switching on/off of the feature needs to be carefully controlled.
Another solution for reducing static power consumption is the use of state retention power gated (SRPG) cells in which 90% of the memory cells are always switched off. Typically, SPRG cells include latches powered by two power rails where one of the power rails is always switched on and the other is switched off for 90% of the memory cell operation. However, the timing critical nature of the above solution makes it unsuitable for automotive applications since there may be several timing violations in the automotive environment due to supply noise. Additionally, the use of multiple power rails complicates the layout of the IC. It would be advantageous to be able to reduce static power consumption of ICs that are used in hostile environments.